1. Field of the Invention
This invention relates to computer systems and more particularly to interrupt control architectures and schemes employed within symmetrical multiprocessing systems.
2. Description of the Relevant Art
Computer systems employing multiple processing units hold a promise of economically accommodating performance capabilities that surpass those of current single-processor based systems. Within a multiprocessing environment, rather than concentrating all the processing for an application in a single processor, tasks are divided into groups or "threads" that can be handled by separate processors. The overall processing load is thereby distributed among several processors, and the distributed tasks may be executed simultaneously in parallel. The operating system software divides various portions of the program code into the separately executable threads, and typically assigns a priority level to each thread.
FIG. 1 is a block diagram of a so-called symmetrical multiprocessing system 10 including a plurality of processing units 12A-12C. Each processing unit 12A-12C includes a processing core 14A-14C, a cache memory 16A-16C, and a bus interface 18A-18C, respectively. The processing units 12A-12C are coupled to a main memory 20 via a system bus 22. A pair of I/O devices 24 and 26 are further coupled to system bus 22.
The multiprocessing system 10 of FIG. 1 is symmetrical in the sense that all processing units 12A-12C share the same memory space (i.e., main memory 20) and access the memory space using the same address mapping. The multiprocessing system 10 is further symmetrical in the sense that all processing units 12A-12C share equal access to the same I/O subsystem.
In general, a single copy of the operating system software as well as a single copy of each user application file is stored within main memory 20. Each processing unit 12A-12C executes from these single copies of the operating system and user application files. Although processing cores 14A-14C may be executing code simultaneously, it is noted that only one of the processing units 12A-12C may assume mastership of the system bus 22 at a given time. Thus, a bus arbitration mechanism (not shown) is provided to arbitrate concurrent bus requests of two or more processing units and to grant mastership to one of the processing units based on a predetermined arbitration algorithm. A variety of bus arbitration techniques are well-known.
The high speed cache memory 16A-16C of each processing unit 12A-12C, respectively, stores data most recently accessed by the respective processing unit along with address tags that indicate the main memory address to which the associated data corresponds. Since programs tend to execute the same sections of code and access the same data structures repeatedly, many of the locations accessed will already be stored in the cache if the cache is sufficiently large.
The cache mechanisms provide two significant benefits. First, because the caches are implemented with high-speed memory and can be accessed without bus arbitration and buffer delays, an access to a location stored in a respective cache is much faster than a main memory access. Second, because an access to a location stored in the respective cache does not require access to the system bus, the bus utilization of each processor is greatly reduced. The system bus is therefore available to service other requested transactions. Typically, the higher the "hit rate", the better the overall system performance. The hit rate is the percentage of accesses by a particular processing core that are to locations already stored in the cache. Well designed systems with moderately large caches can achieve hit rates of over ninety percent.
An important consideration with respect to multiprocessing systems that employ cache memories is data coherency. Since multiple copies of the data (and instructions) stored by main memory 20 may concurrently reside in one or more of the cache memories 16A-16C, a specialized mechanism must be employed to maintain the integrity of data in the event that one of the memory subsystems is updated (i.e., written with new data). For example, consider a situation wherein a particular section of data is updated within cache memory 16A by processing core 14A but is not updated within the corresponding section of main memory 20. If processing core 14B subsequently accesses the same section of code, there must be some reliable mechanism to track which section is up-to-date and which section is no longer valid to ensure that processing core 14B accesses the proper data. A variety of techniques have therefore been developed with the goal of efficiently maintaining cache coherency, including those based on so-called write-through and write-back techniques. Various cache coherency techniques are described within a host of publications of the known prior art, and are not discussed further herein.
Another important consideration with respect to symmetrical multiprocessing systems is the handling and distribution of interrupts generated by various system resources. For example, in the system of FIG. 1, I/O devices 24 and 26 may each assert a respective interrupt signal based on the occurrence (or non-occurrence) of a particular event. As will be appreciated by those of skill in the art, interrupts are routinely generated by system resources such as keyboard devices, printers, and timers, among other things. Many systems also accommodate software interrupts whereby an interrupt may be asserted in response to software command. Due to the number of different interrupts that may occur within a system, it is desirable to provide a mechanism to efficiently manage and distribute the interrupts to achieve optimal system performance and bus utilization.
One technique for handling interrupts employs a centralized interrupt controller that is capable of receiving a plurality of interrupts and of prioritizing and distributing the interrupts amongst the various processing units. A problem associated with a centralized interrupt control technique is that the total number of interrupts which can be accommodated is typically limited by the number of input pins provided to the centralized interrupt controller. In other words, for example, if the centralized interrupt controller includes a total of sixteen interrupt input pins, greater than sixteen interrupt generating devices typically cannot be accommodated within the system. This limits system flexibility. Furthermore, within such systems a dedicated interrupt line must be connected to each interrupt source. Such dedicated interrupt lines may not be available on remote cabling networks that connect one or more peripherals to the computer system. Again, system flexibility may consequently be limited.
Another problem which may be encountered with respect to interrupt management within symmetrical multiprocessing systems is the occurrence of invalid or "spurious" interrupts. As is generally known, when a level triggered interrupt is being serviced by a designated processing unit, an I/O command is typically associated with the interrupt service routine that, where executed, causes the interrupt source to deassert the interrupt signal. Subsequently, an End Of Interrupt (EOI) command is executed to inform the interrupt controller that the interrupt service has completed. A spurious interrupt may occur if a significant latency is introduced between the time at which the processing unit executes the I/O command (to cause the interrupt source to deassert the interrupt signal) and the time at which the interrupt signal is actually deasserted. Such a latency may occur, for example, if the I/O device resides on a remote bus via several bus bridge units. If the interrupt source does not deassert the interrupt signal before the centralized interrupt controller responds to the End Of Interrupt command, the continued assertion of the interrupt may be detected by the interrupt controller, thus causing the interrupt to unintentionally re-initiate.
The management of timer tick interrupts poses another problem within symmetrical multiprocessing systems. As is generally known, in a multiprocessing system there are some interrupts which need to be handled by all processing units in a broadcast fashion. For example, many multiprocessing systems use the timer tick interrupt to signal the end of a time slice and to thus cause each processing unit to execute a task switch. This is typically accomplished by either simultaneously sending the timer tick interrupt to all processing units or by sending the timer tick interrupt to the first processing unit in the chain and passing it to the others via interprocessor interrupts (IPIs). However, there are drawbacks to both of these schemes. If all processing units are interrupted at the same time, they will attempt to access the same shared interrupt handler code and will lock shared system resources at the same time. This may cause a great deal of contention and may require some processing units to wait until the required resources become available. If the timer tick interrupt is provided to the first processing unit in the chain and is passed to the others by using interprocessor interrupts, increased software overhead and bus utilization is incurred.
Still additional problems related to interrupt management within symmetrical multiprocessing systems include the integration of system management interrupts (SMI) and the prioritization of interrupts. It is desirable to provide mechanisms within symmetrical multiprocessing systems that allow both efficient integration of SMI interrupts within the system as well as flexible interrupt prioritization.